Mixed HDL on Fomu¶
It is strongly suggested to get familiar with Verilog on Fomu and VHDL on Fomu examples before tinkering with these mixed language use cases.
“Hello world!” - Blink a LED¶
The canonical “Hello, world!” of hardware is to blink a LED. The directory hdl/mixed/blink contains a VHDL + Verilog example of a blink project. This takes the 48 MHz clock and divides it down by a large number so you get an on/off pattern.
Enter the hdl/mixed/blink directory and build the demo by using
You can then load
blink.dfu onto Fomu by using
make load or the same
dfu-util -D command we’ve been using so
You should see a blinking pattern of varying color on your Fomu, indicating your bitstream was successfully loaded.
If you take a closer look at the sources in hdl/mixed/blink, you will find that
clkgen are written both in VHDL and Verilog.
The Makefile uses
clkgen.v by default.
However, any of the following cases produce the same result:
You can modify variables
VERILOG_SYN_FILES in the Makefile
for trying other combinations.
For a better understanding, it is suggested to compare these modules with the single file solutions in
Verilog on Fomu and VHDL on Fomu.